This paper presents a full duplex, real time implementation of ITU-T G.723.1 [7,8] speech coder using the TMS320C5402 DSP chip which is based on a 16 bit fixed-point architecture. An optimization method is proposed in order to reduce the total necessary cycle time consumed in real-time implementation. The Multi-Pulse Maximum Likelihood Quantization (MP-MLQ) excitation search block which is the most computation-intensive block in the coder is restructured to reduce the algorithmic redundancy. In addition, efficient filtering methods and memory management are used for further optimization. The bit-exact verification with the ITU test vectors and performance evaluation aspects are also discussed in this paper.